2 #include <avr/interrupt.h>
4 #include <util/delay.h>
5 #include <util/atomic.h>
9 #define PWM_STEP_SHIFT 2 /* sub-LSB precision */
10 #define PWM_TOP (((PWM_MAX) + (4 << (PWM_STEP_SHIFT))) >> (PWM_STEP_SHIFT))
12 #error PWM_TOP too high
15 volatile unsigned char channels_running;
17 static uint16_t pwm[N_PWMLEDS];
18 static volatile unsigned char step;
19 static unsigned char pll_enabled;
21 static void enable_pll()
26 /* Synchronize to the phase lock */
28 while ((PLLCSR & _BV(PLOCK)) == 0)
43 for (i = 0; i < N_PWMLEDS; i++)
46 // PWM channel D is inverted, ...
47 TCCR1C = _BV(COM1D1) | _BV(COM1D0) | _BV(PWM1D);
48 // PWM channels A and B are not
49 TCCR1A = _BV(COM1A1) | _BV(COM1B1) | _BV(PWM1A) | _BV(PWM1B);
51 TCCR1B = _BV(CS10); // no clock prescaling
54 OCR1C = PWM_TOP & 0xFF; // TOP value
56 TC1H = PWM_TOP >> 8; // PWM3 is inverted
57 OCR1D = PWM_TOP & 0xFF;
60 OCR1B = OCR1A = 0; // initial stride is 0
62 DDRB &= ~(_BV( PB1 ) | _BV( PB3 ) | _BV( PB5 )); // tristate it
63 PORTB &= ~(_BV( PB1 ) | _BV( PB3 ) | _BV( PB5 )); // set to zero
70 for (i = 0; i < N_PWMLEDS; i++)
73 DDRB &= ~(_BV( PB1 ) | _BV( PB3 ) | _BV( PB5 ));
74 TCCR1D = TCCR1C = TCCR1B = TCCR1A = 0;
78 PLLCSR &= ~(_BV(PLLE) | _BV(PCKE));
81 void pwm_off(unsigned char n)
83 ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {
85 channels_running &= ~(1 << n);
88 case 0: DDRB &= ~_BV(PB1); break;
89 case 1: DDRB &= ~_BV(PB3); break;
90 case 2: DDRB &= ~_BV(PB5); break;
95 static void pwm_update_hw(unsigned char n)
98 uint16_t stride = (pwm[n] + step) >> PWM_STEP_SHIFT;
101 stride = PWM_TOP - stride;
122 void pwm_set(unsigned char n, uint16_t stride)
124 if (stride > PWM_MAX)
127 ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {
129 channels_running |= (1 << n);
132 power_timer1_enable();
139 case 0: DDRB |= _BV(PB1); break;
140 case 1: DDRB |= _BV(PB3); break;
141 case 2: DDRB |= _BV(PB5); break;
150 if (++step >= (1 << PWM_STEP_SHIFT))
153 for (i = 0; i < N_PWMLEDS; i++)
158 void pwm_disable_if_not_needed()
160 if (channels_running)
164 DDRB &= ~(_BV(PB1) | _BV(PB3) | _BV(PB5));
165 PLLCSR &= ~(_BV(PLLE) | _BV(PCKE));
167 power_timer1_disable();