]> www.fi.muni.cz Git - clock.git/commit
Initial import master
authorJan "Yenya" Kasprzak <kas@fi.muni.cz>
Thu, 28 Nov 2013 22:39:10 +0000 (23:39 +0100)
committerJan "Yenya" Kasprzak <kas@fi.muni.cz>
Thu, 28 Nov 2013 22:39:10 +0000 (23:39 +0100)
commite53ccd0194c9b81edcc845fa34a499c18bef1976
tree051daa866286869511211df1722450c63fb6c57c
Initial import
schematics/SSR.fp [new file with mode: 0644]
schematics/atmega48_88_168.sym [new file with mode: 0644]
schematics/clock.sch [new file with mode: 0644]
schematics/gafrc [new file with mode: 0644]
schematics/pins.txt [new file with mode: 0644]
schematics/s202s01-ssr-1.sym [new file with mode: 0644]