#define PWM_STEP_SHIFT 2 /* sub-LSB precision */
#define PWM_TOP (((PWM_MAX) + (4 << (PWM_STEP_SHIFT))) >> (PWM_STEP_SHIFT))
-#if PWM_TOP > 0x3FF
+#if PWM_TOP > 0x0FF
#error PWM_TOP too high
#endif
enable_pll();
- // PWM channel D is inverted, ...
- TCCR1C = _BV(COM1D1) | _BV(COM1D0) | _BV(PWM1D);
- // PWM channels A and B are not
- TCCR1A = _BV(COM1A1) | _BV(COM1B1) | _BV(PWM1A) | _BV(PWM1B);
- TCCR1D = 0;
- TCCR1B = _BV(CS10); // no clock prescaling
+ TCCR1 = _BV(CTC1) | _BV(CS10); // no clock prescaling
+ GTCCR = _BV(COM1A1) | _BV(COM1B1) | _BV(PWM1A) | _BV(PWM1B);
- TC1H = PWM_TOP >> 8;
- OCR1C = PWM_TOP & 0xFF; // TOP value
+ OCR1C = PWM_TOP;
+ OCR1A = OCR1B = 0; // initial stride is 0
- TC1H = PWM_TOP >> 8; // PWM3 is inverted
- OCR1D = PWM_TOP & 0xFF;
-
- TC1H = 0x00;
- OCR1B = OCR1A = 0; // initial stride is 0
-
- DDRB &= ~(_BV( PB1 ) | _BV( PB3 ) | _BV( PB5 )); // tristate it
- PORTB &= ~(_BV( PB1 ) | _BV( PB3 ) | _BV( PB5 )); // set to zero
+ DDRB &= ~(_BV( PB1 ) | _BV( PB4 )); // tristate it
+ PORTB &= ~(_BV( PB1 ) | _BV( PB4 )); // set to zero
}
+#if 0
void susp_pwm()
{
unsigned char i;
PLLCSR &= ~(_BV(PLLE) | _BV(PCKE));
}
+#endif
void pwm_off(unsigned char n)
{
switch (n) {
case 0: DDRB &= ~_BV(PB1); break;
- case 1: DDRB &= ~_BV(PB3); break;
- case 2: DDRB &= ~_BV(PB5); break;
+ case 1: DDRB &= ~_BV(PB4); break;
}
}
}
static void pwm_update_hw(unsigned char n)
{
- unsigned char hi, lo;
uint16_t stride = (pwm[n] + step) >> PWM_STEP_SHIFT;
- if (n == 2)
- stride = PWM_TOP - stride;
-
- hi = stride >> 8;
- lo = stride & 0xFF;
-
switch (n) {
case 0:
- TC1H = hi;
- OCR1A = lo;
+ OCR1A = stride;
break;
case 1:
- TC1H = hi;
- OCR1B = lo;
- break;
- case 2:
- TC1H = hi;
- OCR1D = lo;
+ OCR1B = stride;
break;
}
}
switch(n) {
case 0: DDRB |= _BV(PB1); break;
- case 1: DDRB |= _BV(PB3); break;
- case 2: DDRB |= _BV(PB5); break;
+ case 1: DDRB |= _BV(PB4); break;
}
}
}