pwm.c: PLL clock enabling code

- factored out from init_pwm() in order to be able to suspend PLL also
	during normal operation
- use _delay_us(100) instead of _delay_ms(1) as recommended by datasheet
- disable PLL in susp_pwm()

diff --git a/firmware/pwm.c b/firmware/pwm.c
index b9b42c926cbd49cd449d36a76986bcdbc494b24d..3ef52c3fd436bc733ab7567b722487981fd3c133 100644 (file)
--- a/firmware/pwm.c
+++ b/firmware/pwm.c
@@ -7,6 +7,18 @@
 static uint16_t pwm[N_PWMLEDS];
 static volatile unsigned char step;
 
+static void enable_pll()
+{
+       /* Async clock */
+       PLLCSR = _BV(PLLE);
+
+       /* Synchronize to the phase lock */
+       _delay_us(100);
+       while ((PLLCSR & _BV(PLOCK)) == 0)
+               ;
+       PLLCSR |= _BV(PCKE);
+}
+
 void init_pwm()
 {
        int i;
@@ -16,14 +28,7 @@ void init_pwm()
        for (i = 0; i < N_PWMLEDS; i++)
                pwm[i] = 0;
 
-       /* Async clock */
-       PLLCSR = _BV(PLLE);
-
-       /* Synchronize to the phase lock */
-       _delay_ms(1);
-       while ((PLLCSR & _BV(PLOCK)) == 0)
-               ;
-       PLLCSR |= _BV(PCKE);
+       enable_pll();
 
        // PWM channel D is inverted, ...
        TCCR1C = _BV(COM1D1) | _BV(COM1D0) | _BV(PWM1D);
@@ -56,6 +61,8 @@ void susp_pwm()
        TCCR1D = TCCR1C = TCCR1B = TCCR1A = 0;
        TIMSK = 0;
        TIFR = 0;
+
+       PLLCSR &= ~(_BV(PLLE) | _BV(PCKE));
 }
 
 void pwm_off(unsigned char n)