Precise monitoring of network traffic can help a lot of network applications to improve their functionality. By network monitoring, applications can obtain a better conception concerning flows and packets on the network. In consequence, execution of network applications can be realised more effectively with such knowledge. To satisfy needs of high-speed network monitoring, we have developed a hardware accelerated netflow probe FlowMon which collects data about the network traffic and provides them to the application layer. FlowMon hardware design contains memories configured in a hierarchy which is similar to common computer architectures. In order to find the optimal configuration of such a memory hierarchy in FlowMon, we have analysed information about temporal and spacial localisation of packets in real network traffic. Especially, we developed a simulation model of the cache memory, which, if employed appropriately, can speed up the netflow processing in FlowMon. In this report we present our results regarding simulation of the cache memory. These results make a crucial framework which helps hardware designers to justify the FlowMon design.